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DARPA, Intel Partner to Advance Domestic Development of ASICs


DARPA, Intel Partner to Advance Domestic Development of ASICs

The Defense Advanced Research Projects Agency has partnered with Intel to advance the domestic development of application-specific integrated circuit platforms.

ASICs are specialized integrated circuits designed to excel in a specific task rather than be used for general purposes.

The three-year Structured Array Hardware for Automatically Realized Applications partnership will enable the design of ASICs that include high-end security countermeasures, Intel said Thursday.

Jose Roberto Alvarez, a senior executive in Intel’s programmable solutions group, said the partnership will take advantage of the eASIC technology, which functions as an intermediary between FPGAs and standard-cell ASICs.

According to Intel, eASIC technology is less expensive and more power-efficient than FPGAs while having a shorter time-to-market than standard-cell ASICs.

Alvarez said SAHARA will allow defense and commercial electronics developers to deploy custom chips based on Intel’s 10 nm semiconductor process.

Intel said most Department of Defense applications rely on field-programmable gate array platforms, which are designed to be configured after manufacturing.

Using ASIC technology in existing and future applications will provide significantly higher performance and lower power consumption, Intel said.

The SAHARA partnership is aimed at taking advantage of automation and modern security technologies to shorten the time it takes to design ASIC tools, according to Serge Leef, a program manager in DARPA’s Microsystems Technology Office.

Intel said it will work with the University of Florida, Texas A&M University and the University of Maryland in developing security countermeasure technologies to protect data and intellectual property from reverse engineering and counterfeiting.

The universities will use a robust validation process and new attack strategies to test the security of the ASIC chips, Intel added.

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Category: Defense and Intelligence

Tags: 10 nm ASIC DARPA Defense and Intelligence Department of Defense eASIC FPGA Intel Jose Roberto Alvarez Microsystems Technology Office SAHARA semiconductor Serge Leef Texas A&M University University of Florida University of Maryland